Interconnect structure with hybrid barrier layer

An integrated chip comprising:

• a lower conductive wire between sidewalls of a first dielectric layer;
• a second dielectric layer over the first dielectric layer;
• a conductive via over and coupled to the lower conductive wire and between sidewalls of the second dielectric layer;
• a conductive liner layer lining sidewalls and a lower surface of the conductive via;
• and
• a barrier layer lining sidewalls of the conductive liner layer and lining sidewalls of the second dielectric layer, wherein a lower surface of the barrier layer is spaced over a topmost surface of the lower conductive wire.

An integrated chip comprising:

• a lower conductive wire between sidewalls of a first dielectric layer;
• a second dielectric layer over the first dielectric layer;
• a conductive via over and coupled to the lower conductive wire and between sidewalls of the second dielectric layer;
• a barrier layer between sidewalls of the conductive via and the sidewalls of the second dielectric layer;
• and
• a conductive liner layer between sidewalls of the barrier layer and the sidewalls of the conductive via, the conductive liner layer extending along a bottommost surface of the conductive via and a topmost surface of the lower conductive wire.