Semiconductor structure and method for manufacturing the same

A method for manufacturing a semiconductor structure, comprising:

• forming fins over a substrate, wherein each of the fins comprises a fin structure protruded from the substrate and a stack portion having first semiconductor layers and second semiconductor layers alternatingly stacked over the fin structure;
• forming a liner layer over the fins and the substrate;
• forming a doped oxide layer over the liner layer;
• forming a dielectric material over the doped oxide layer;
• etching the liner layer, the doped oxide layer, and the dielectric material to form an isolation structure between the fins;
• forming an isolation feature over and interfacing the dielectric material of the isolation structure;
• forming a dummy gate structure over the fins and the isolation feature;
• forming source/drain features in the fins;
• removing dummy gate structure and the first semiconductor layers to form gate trenches;
• and
• forming gate structures in the gate trenches, wherein the gate structures interface the liner layer and the doped oxide layer of the isolation structure.

A method for manufacturing a semiconductor structure, comprising:

• forming fins over a substrate, wherein each of the fins comprises a fin structure protruded from the substrate and a stack portion having first semiconductor layers and second semiconductor layers alternatingly stacked over the fin structure;
• forming an isolation structure between the fins, wherein the isolation structure has a first liner layer on sidewalls of the fin structures and over the substrate, a second liner layer having first dopants over the first liner layer, and a dielectric material over the second liner layer;
• forming a cladding layer over and interfacing the first liner layer and the second liner layer of the isolation structure;
• forming an isolation feature over and interfacing the dielectric material of the isolation structure;
• forming a dummy gate structure over the fins and the isolation feature;
• forming source/drain features in the fins;
• removing dummy gate structure, the first semiconductor layers, and the cladding layer;
• and
• forming gate structures wrapping around the second semiconductor layers, wherein a top surface of the isolation feature is higher than top surfaces of the gate structures.