Semiconductor structure including field effect transistor with scaled gate length and method

A structure comprising:

• a substrate;
• a field effect transistor on the substrate and including:
• a semiconductor fin;
• a gate structure including:
• a first portion on a top surface and opposing sides of the semiconductor fin;
• and a second portion on the first portion, wherein the second portion includes:
• a gate dielectric layer;
• and a gate conductor layer on the gate dielectric layer and further has an edge region that extends laterally beyond the first portion, and wherein the first portion includes an additional gate dielectric layer between the semiconductor fin and the gate dielectric layer;
• and
• gate sidewall spacers adjacent to opposing sides of the gate structure, wherein each gate sidewall spacer has a first section and a second section, wherein the first section is positioned laterally adjacent to the first portion of the gate structure between the edge region of the second portion of the gate structure and the semiconductor fin, and wherein the second section is positioned laterally adjacent to the first section and to the second portion of the gate structure;
• and
• an additional field effect transistor on the substrate, wherein the additional field effect transistor includes an additional gate structure with a longer effective gate length than the gate structure.

A method comprising:

• providing a substrate;
• and
• forming, on the substrate, a structure including:
• a semiconductor body;
• a gate structure including:
• a first portion on the semiconductor body and a second portion on the first portion, wherein the second portion includes:
• a gate dielectric layer;
• and a gate conductor layer and further has an edge region that extends laterally beyond the first portion, and wherein the first portion includes an additional gate dielectric layer between the semiconductor body and the gate dielectric layer;
• and
• gate sidewall spacers adjacent to opposing sides of the gate structure, wherein each gate sidewall spacer has a first section and a second section, wherein the first section is positioned laterally adjacent to the first portion of the gate structure between the edge region of the second portion of the gate structure and the semiconductor body, and wherein the second section is positioned laterally adjacent to the first section and to the second portion of the gate structure.