Isolation Structure and Methods of Forming Same

A method, comprising:

• forming a stack of channel layers and sacrificial layers over a fin base, wherein the sacrificial layers include a top portion and a bottom portion below the top portion;
• forming an isolation feature disposed adjacent to the fin base and the stack;
• forming a dummy gate structure disposed over the stack and the isolation feature;
• forming a source/drain trench in the fin base and exposing sidewalls of the sacrificial layers;
• selectively removing the top portion of the sacrificial layers to form a top opening and the bottom portion of the sacrificial layers to form a bottom opening;
• depositing a dummy layer in the top opening and the bottom opening;
• selectively and partially recessing the dummy layer to form inner spacer recesses among the channel layers;
• forming inner spacer features in the inner spacer recesses;
• forming a source/drain feature in the source/drain trench;
• and
• replacing the dummy gate structure and the dummy layer in the top opening but not the dummy layer in the bottom opening with a metal gate structure.

A semiconductor structure, comprising:

• a fin base protruding from a substrate;
• two separation layers disposed over the substrate;
• two source/drain features disposed over the two separation layers;
• an isolation structure disposed over the fin base and connecting the two separation layers;
• a stack of semiconductor layers disposed over the isolation structure, wherein the stack of semiconductor layers includes a bottom semiconductor layer and top semiconductor layers disposed over the bottom semiconductor layer, wherein the bottom semiconductor layer connects the two separation layers, and wherein the top semiconductor layers connect the two source/drain features;
• an isolation feature disposed adjacent to the fin base and the isolation structure, wherein a top surface of the isolation feature is above a top surface of the isolation structure;
• and
• a metal gate structure wrapping around the top semiconductor layers.