US 2026/0075889 A1 · HYBRID ISOLATION PILLARS

Abstract

A semiconductor IC device includes a hybrid isolation pillar that has a first isolation pillar and a second isolation pillar. The semiconductor IC device includes a source/drain region in direct contact with the first isolation pillar and in direct contact with the second isolation pillar. The first isolation pillar may be composed of a same or different material relative to the material of the second isolation pillar. The source/drain region may be confined by the first isolation pillar and the second isolation pillar. The hybrid isolation pillar may reduce parasitic capacitance and may reduce a pitch between a n-type transistor and a p-type transistor and may reduce a pitch between the same type transistors within a transistor cell.

Claims20

Dependent claims

A semiconductor integrated circuit (IC) device comprising:

a first isolation pillar and a second isolation pillar;
and
a source/drain region in direct contact with the first isolation pillar and in direct contact with the second isolation pillar.

Dependencies are inferred from the claim text.

Facts

Application

18/828,659Filed 9 Sep 2024

Published

12 Mar 2026

Term ends

Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10D 62/115
Isolations within a component, i.e. internal isolations: dielectric isolations, e.g. air gaps
H10D 84/038
Using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology: using silicon technology, e.g. SiGe
H10D 30/014
Manufacture or treatment: of FETs having zero-dimensional [0D] or one-dimensional [1D] channels, e.g. quantum wire FETs, single-electron…
H10D 30/43
FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels: having one-dimensional [1D] charge…

Hybrid isolation pillars

Life of this patent

Hybrid isolation pillars

Life of this patent

Abstract

Claims20