Pyramid geometry metal gate structure

A semiconductor device comprising:

• a source/drain region;
• a nanostructure adjacent the source/drain region;
• a gate structure around the nanostructure;
• a first inner spacer between the gate structure and the source/drain region, the first inner spacer having a first width;
• and
• a second inner spacer between the gate structure and the source/drain region, the second inner spacer having a second width, the second width being greater than the first width, the first inner spacer and the second inner spacer disposed at opposing sides of the nanostructure.

A method of forming a semiconductor device comprising:

• forming a stack of at least a first set of semiconductor layers and a second set of semiconductor layers;
• replacing the first set of semiconductor layers with disposable layers;
• forming a sidewall spacer along a sidewall of the stack, wherein at least a first portion of the disposable layers is exposed by the sidewall spacer;
• first laterally etching the first portion of the disposable layers that are exposed;
• recessing the sidewall spacer to expose a second portion of the disposable layers;
• second laterally etching the second portion of the disposable layers that are exposed by the sidewall spacer;
• forming inner spacers in recesses formed by the first laterally etching and the second laterally etching of the disposable layers;
• and
• replacing remaining portions of the disposable layers with a gate structure, the gate structure disposed on the second set of semiconductor layers.