Integrated process and processing system for manufacturing pmos transistors

A method of manufacturing an electronic device, the method comprising:

• depositing an interfacial layer comprising silicon oxide (SiOx) on a top surface of a silicon (Si) channel located between a source region and a drain region on a substrate;
• depositing a high-κ dielectric layer comprising hafnium oxide (HfOx) on the interfacial layer;
• depositing a dipole depinning layer on the high-κ dielectric layer;
• performing a low temperature oxygen (O2) and/or nitrogen (N2) annealing process;
• performing a rapid thermal process (RTP), the RTP including one or more of a spike anneal process, a nanosecond anneal process, or a millisecond anneal process;
• depositing a P-metal layer on the dipole depinning layer;
• depositing a capping layer on the P-metal layer;
• and
• selectively removing the capping layer, wherein the method is performed in situ in an integrated processing system, and the low temperature oxygen (O2) and/or nitrogen (N2) annealing process is performed prior to the RTP, or the RTP is performed prior to the low temperature oxygen (O2) and/or nitrogen (N2) annealing process.

A processing system comprising:

• a central transfer station comprising a robot configured to move one or more substrates;
• a plurality of process stations, each process station connected to the central transfer station and providing a processing region separated from processing regions of adjacent process stations;
• and
• a controller connected to the central transfer station and the plurality of process stations, the controller configured to activate the robot to move the one or more substrates between process stations, and the robot configured to perform a method comprising:
• depositing an interfacial layer on a top surface of a channel located between a source region and a drain region on the substrate;
• depositing a high-κ dielectric layer on the interfacial layer;
• depositing a dipole depinning layer on the high-κ dielectric layer;
• depositing a P-metal layer on the dipole depinning layer;
• and
• depositing a capping layer on the P-metal layer, wherein the method is performed in situ.