Nanosheet device backside connecting to both vdd and vss at the same level
AssigneeInternational Business Machines Corporation
InventorsTsung-Sheng Kang, Tao Li, Ruilong Xie, Min Gyu Sung
Life of this patent
Estimating the term…
Abstract
A microelectronic structure includes a first nanosheet FET that includes a first and second source/drain. A second nanosheet FET located adjacent to the first nanosheet FET. A first backside contact connected to the first source/drain and the first backside contact extends through the backside region of the second nanosheet FET. A second backside contact connected to the second source/drain. The first backside contact and the second backside contact are located on the same level.
Claims20
A microelectronic structure comprising:
- a first nanosheet FET that includes a first and second source/drain;
- a second nanosheet FET located adjacent to the first nanosheet FET;
- a first backside contact connected to the first source/drain, wherein the first backside contact extends through a backside region of the second nanosheet FET;
- and
- a second backside contact connected to the second source/drain, wherein the first backside contact and the second backside contact are located on the same level.
A microelectronic structure comprising:
- a first nanosheet FET that includes a first and second source/drain;
- a second nanosheet FET located adjacent to the first nanosheet FET;
- a first backside contact connected to the first source/drain, wherein the first backside contact extends through a backside region of the second nanosheet FET;
- a second backside contact connected to the second source/drain, wherein the first backside contact and the second backside contact are located on the same level;
- and
- a dielectric pillar located between the first backside contact and the second backside contact.
A microelectronic structure comprising:
- a first nanosheet FET that includes a first and second source/drain;
- a second nanosheet FET located adjacent to the first nanosheet FET includes a third source/drain;
- a dielectric cap is located on a backside of the third source/drain;
- a first backside contact connected to the first source/drain, wherein the first backside contact extends through a backside region of the second nanosheet FET;
- a second backside contact connected to the second source/drain, wherein the first backside contact and the second backside contact are located on the same level;
- and
- a dielectric pillar located between the first backside contact and the second backside contact.
Dependencies are inferred from the claim text.