Semiconductor device

A semiconductor device comprising:

• a first conductivity type substrate;
• a first conductivity type epitaxial layer on a first surface of the first conductivity type substrate, and the first conductivity type epitaxial layer including a gate trench;
• the gate trench including
• a plurality of first extensions extending in a first direction,
• a plurality of second extensions extending in a second direction, the second direction intersecting the first direction, and
• a plurality of crossing regions where the plurality of first extensions and the plurality of second extensions intersect each other;
• a gate electrode in the gate trench;
• a gate insulating layer between the first conductivity type epitaxial layer and the gate electrode;
• a source electrode above the first conductivity type epitaxial layer;
• a first conductivity type doping layer between the first conductivity type epitaxial layer and the source electrode, and the first conductivity type doping layer having a first conductivity type;
• a second conductivity type doping layer having a second conductivity type, the second conductivity type being different from the first conductivity type;
• a drain electrode on a second surface of the first conductivity type substrate;
• and
• a barrier pattern overlapping the plurality of crossing regions and the second conductivity type doping layer,
• wherein the barrier pattern includes a plurality of barrier patterns, and each of the plurality of barrier patterns is spaced apart from each other in the first direction and the second direction.

A semiconductor device comprising:

• a first conductivity type substrate;
• a first conductivity type epitaxial layer on a first surface of the first conductivity type substrate, and the first conductivity type epitaxial layer including a gate trench;
• the gate trench including
• a plurality of first extensions extending in a first direction,
• a plurality of second extensions extending in a second direction, the second direction intersecting the first direction, and
• a plurality of crossing regions where the plurality of first extensions and the plurality of second extensions intersect each other;
• a gate electrode in the gate trench;
• a gate insulating layer between the first conductivity type epitaxial layer and the gate electrode;
• a source electrode above the first conductivity type epitaxial layer;
• a first conductivity type doping layer between the first conductivity type epitaxial layer and the source electrode, and the first conductivity type doping layer including a first conductivity type;
• a second conductivity type doping layer is
• at a corner of the first conductivity type doping layer,
• surrounded by the first conductivity type doping layer, and
• having a second conductivity type, the second conductivity type being different from the first conductivity type;
• a drain electrode on a second surface of the first conductivity type substrate;
• and
• a barrier pattern below each of the plurality of crossing regions, and the barrier pattern having the second conductivity type,
• wherein the barrier pattern includes
• a first portion surrounding at least a portion of the plurality of crossing regions, and
• a second portion between the first conductivity type epitaxial layer and the second conductivity type doping layer.