Semiconductor device including air gap

A manufacturing method of a semiconductor device, the manufacturing method comprising:

• forming an active pattern extending in a first direction in a substrate;
• forming first and second sacrificial gate structures extending in a second direction intersecting the first direction and spaced apart from each other in the first direction in the substrate, and forming gate spacers on sidewalls of each of the first and second sacrificial gate structures;
• forming a source/drain region by recessing the active pattern exposed on both sides of the gate spacers between the first and second sacrificial gate structures;
• forming an interlayer insulating layer covering the gate spacers and the source/drain region;
• removing the first and second sacrificial gate structures and forming first and second gate structures respectively including a gate insulating layer, a gate electrode on the gate insulating layer, and a gate capping layer on the gate spacers, the gate insulating layer, and the gate electrode;
• forming a first sacrificial interlayer insulating layer over the interlayer insulating layer and the first and second gate structures;
• forming a preliminary contact structure penetrating the interlayer insulating layer and the first sacrificial interlayer insulating layer to contact the source/drain region;
• etching the preliminary contact structure in a vertical direction to form a contact structure having an upper surface at a level lower than the first and second gate structures;
• and
• forming a contact insulating layer contacting portions of sidewalls of the first and second gate structures exposed from the contact structure.

A manufacturing method of a semiconductor device, the manufacturing method comprising:

• forming an active pattern extending in a first direction in a substrate;
• forming first and second gate structures extending in a second direction intersecting the first direction and spaced apart from each other in the first direction, each of the first and second gate structures including a gate electrode, gate spacers on both sides of the gate electrode, and a gate capping layer on the gate electrode and the gate spacers;
• recessing portions of the active pattern exposed on both sides of the gate spacers to form first to third source/drain regions spaced apart from each other in the first direction;
• forming an interlayer insulating layer covering the first to third source/drain regions;
• forming first to third contact structures spaced apart from each other in the first direction and penetrating the interlayer insulating layer to contact the respective first to third source/drain regions;
• etching the second contact structure in a vertical direction to form a recess region exposing an upper surface of the etched second contact structure and sidewalls of the first and second gate structures facing each other across the second contact structure;
• and
• forming a contact insulating layer in the recess region,
• wherein upper surfaces of the first and third contact structures are coplanar with upper surfaces of the first and second gate structures and an upper surface of the contact insulating layer.