Semiconductor device having selection elements

A semiconductor device comprising:

• a cell area including a first sub-cell area and a second sub-cell area;
• a first peripheral circuit area adjacent to a first side of the cell area in a first direction;
• and
• a second peripheral circuit area adjacent to a second side of the cell area in a second direction perpendicular to the first direction,
• wherein:
• the first sub-cell area includes a first memory cell disposed closer to the first and second peripheral circuit areas than the second memory cell;
• the second sub-cell area includes a second memory cell disposed farther from the first and second peripheral circuit areas;
• the first memory cell includes a first selection element layer and the second memory cell includes a second selection element layer, each of the first and second selection element layers including a dielectric material containing a dopant;
• and
• a dopant concentration of the first selection element layer is lower than a dopant concentration of the second selection element layer.