Semiconductor memory device

A semiconductor memory device comprising:

• a bitline that extends in a first direction on a substrate;
• an active pattern disposed on the bitline, the active pattern comprising a first sidewall and a second sidewall opposite to each other in the first direction, the active pattern comprising a first surface and a second surface opposite to each other in a vertical direction that is perpendicular to the substrate, wherein the first surface of the active pattern is electrically connected to the bitline;
• a wordline that is on the first sidewall of the active pattern and extends in a second direction;
• a back gate electrode that is on the second sidewall of the active pattern and extends in the second direction;
• a first gate shielding pattern between the wordline and the bitline;
• a second gate shielding pattern between the back gate electrode and the bitline;
• and
• a data storage pattern that is on the active pattern and electrically connected to the second surface of the active pattern,
• wherein at least one of the first gate shielding pattern and the second gate shielding pattern comprises phosphorus silicate glass (PSG).

A semiconductor memory device comprising:

• a peri-gate structure on a substrate;
• a first bonding pad on the peri-gate structure;
• a second bonding pad that is on and contacts the first bonding pad;
• a bitline that is on the second bonding pad and extends in a first direction;
• a shielding conductive pattern that is on the second bonding pad, is adjacent to the bitline, extends in the first direction, and comprises a plurality of shielding conductive line patterns;
• a first wordline that is on the bitline and the shielding conductive pattern and extends in a second direction;
• a second wordline that is on the bitline and the shielding conductive pattern, extends in the second direction, and is spaced apart from the first wordline in the first direction;
• a back gate electrode that is between the first wordline and the second wordline and extends in the second direction;
• a first active pattern that is on the bitline and is between the first wordline and the back gate electrode;
• a second active pattern that is on the bitline and is between the second wordline and the back gate electrode;
• a first gate shielding pattern that is between the first wordline and the bitline, is between the second wordline and the bitline, and comprises an insulating material that is doped with phosphorus (P);
• and
• a data storage pattern electrically connected to the first active pattern and the second active pattern.