Multi-wafer stacked cmos image sensor structure

A method for manufacturing a stacked CMOS image sensor (CIS) structure, the method comprising:

• forming a first die comprising:
• a photodiode comprising an anode electrically connected to a first reference voltage and a cathode;
• a transfer gate comprising a first terminal electrically connected to the cathode of the photodiode and a second terminal electrically connected to a first floating node;
• a first reset switch electrically connected between the first floating node and a second reference voltage;
• and
• forming a second die comprising:
• a selective conversion gain (SCG) switch electrically connected between the first floating node and a second floating node;
• a SCG diffusion capacitor electrically connected between the first reference voltage and the second floating node;
• a second reset switch electrically connected between the second floating node and the second reference voltage;
• a source follower transistor comprising a gate terminal electrically connected to the first floating node, a drain terminal connected to the second reference voltage and a source terminal;
• and
• a row select switch connected between the source terminal of the source follower transistor and a third floating node,
• wherein the second die further comprises a gull-wing type metal-insulator-metal (MIM) capacitor with a prominent bend in the wing inner section towards the wing root;
• and;
• forming a third die comprising an image sensing circuit electrically connected to the third floating node;
• stacking the first die, the second die and the third die in to the stacked CIS structure.

A stacked CMOS image sensor (CIS) structure, comprising:

• a first die comprising:
• a plurality of photodiodes comprising an anode electrically connected to a first reference voltage and a cathode;
• a plurality of transfer gates comprising a first terminal electrically connected to the cathode of the photodiode and a second terminal electrically connected to a first floating node;
• a first reset switch electrically connected between the first floating node and a second reference voltage;
• and
• a floating node diffusion capacitor electrically connected between the first reference voltage and the first floating node, wherein the floating node diffusion capacitor comprises a P-N junction formed between a p-type implant and an n-type implant;
• a second die comprising:
• a selective conversion gain (SCG) switch electrically connected between the first floating node and a second floating node;
• a SCG diffusion capacitor electrically connected between the first reference voltage and the second floating node, wherein the SCG diffusion capacitor is a gull-wing type metal-insulator-metal (MIM) capacitor with a prominent bend in the wing inner section towards the wing root;
• a second reset switch electrically connected between the second floating node and the second reference voltage;
• a source follower transistor comprising a gate terminal electrically connected to the first floating node, a drain terminal connected to the second reference voltage and a source terminal;
• and
• a row select switch connected between the source terminal of the source follower transistor and a third floating node;
• and
• a third die comprising an image sensing circuit electrically connected to the third floating node.