Fused instruction to accelerate performance of secure hash algorithm 2 (sha-2) workloads in a graphics environment

A method comprising:

• receiving, by an execution resource of a graphics processor, a fused secure hash algorithm (SHA) instruction identifying a length corresponding to a data size of the fused SHA instruction and a functional control identifying an operation type of the fused SHA instruction;
• decoding the fused SHA instruction to identify, based on a combination of the length value and the function control value identified in the fused SHA instruction, a sub-function of the fused SHA instruction, wherein the sub-function is one of multiple sub-functions available for the fused SHA instruction;
• based on decoding the fused SHA instruction, causing, by the execution resource, the sub-function identified by the length and the function control to be scheduled to an integer pipeline of the execution resource;
• and
• executing, by execution circuitry of the execution resource, the sub-function of the fused SHA instruction in an integer pipeline of the execution circuitry, the sub-function to perform merged operations on a source operand of the fused SHA instruction, wherein the integer pipeline of the execution circuitry comprises wiring and xor circuitry to implement the merged operations comprising a rotate operation, a shift operation, and an xor operation.

A system comprising:

• a memory to store a block of data;
• and
• a processor coupled to the memory, the processor comprising processing resources, the processing resources comprising execution circuitry to:
• receive a fused secure hash algorithm (SHA) instruction identifying a length corresponding to a data size of the fused SHA instruction and a functional control identifying an operation type of the fused SHA instruction;
• decode the fused SHA instruction to identify, based on a combination of the length value and the function control value identified in the fused SHA instruction, a sub-function of the fused SHA instruction, wherein the sub-function is one of multiple sub-functions available for the fused SHA instruction;
• based on decoding the fused SHA instruction, cause the sub-function identified by the length and the function control to be scheduled to an integer pipeline of the execution resource;
• and
• execute the sub-function of the fused SHA instruction in an integer pipeline of the execution circuitry, the sub-function to perform merged operations on a source operand of the fused SHA instruction, wherein the integer pipeline of the execution circuitry comprises wiring and xor circuitry to implement the merged operations comprising a rotate operation, a shift operation, and an xor operation.