Data processing method and apparatus
AssigneeHuawei Technologies Co., Ltd.
InventorsJian YU, Ming GAN
Life of this patent
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Abstract
Embodiments of this application provide a data processing method and apparatus, to scramble, by using one interleaver or one LDPC tone mapper, a bit sequence of a bitstream of a user to whom a plurality of RUs are allocated, so that hardware costs are reduced. The method includes: allocating a coded bitstream of a first user to M RUs or a first RU including M RUs, where the M RUs or the first RU is an RU allocated to the first user, and M is a positive integer greater than 1; reordering all bits in the coded bitstream by using a first interleaver or a first tone mapper.
Claims24
A data processing method, comprising:
- obtaining a reordered coded bitstream allocated to a first resource unit (RU) for a first user, the first RU comprises M RUs, and M is an integer greater than 1;
- and
- restoring a sequence of bits in the reordered coded bitstream by using a first deinterleaver, wherein a number of data subcarriers (NSD) of the first deinterleaver is a positive integer within [NSD_min/Q, NSD_SD max/Q], wherein NSD_min is a sum of data subcarriers in the first RU, NSD_max is a sum of subcarriers in the first RU, and Q is a number of data subcarriers to which one data bit is mapped.
A data processing method, comprising:
- obtaining a reordered coded bitstream allocated to a first resource unit (RU) for a first user, the first RU comprises M RUs, and M is a integer greater than 1;
- and
- restoring a sequence of bits in the reordered coded bitstream by using a first tone demapper, wherein a number of data subcarriers (NSD) of the first tone demapper is a positive integer within [NSD_min/Q, NSD_max/Q], wherein NSD_min is a sum of data subcarriers comprised in the first RU, NSD_max is a sum of subcarriers comprised in the first RU, and Q is a number of data subcarriers to which a bit is mapped.
A data processing apparatus, comprising:
- at least one processor;
- and
- one or more memories coupled to the at least one processor and storing programming instructions for execution by the at least one processor to:
- cause an interface to obtain a reordered coded bitstream allocated to a first resource unit (RU) for a first user, the first RU comprises M RUs, and M is an integer greater than 1;
- and
- cause a first deinterleaver to restore a sequence of bits in the reordered coded bitstream, wherein a number of data subcarriers (NSD) of the first deinterleaver is a positive integer within [NSD_min/Q, NSD_max/Q], wherein NSD_min is a sum of data subcarriers in the first RU, NSD_max is a sum of subcarriers in the first RU, and Q is a number of data subcarriers to which one data bit is mapped.
A data processing apparatus, comprising:
- at least one processor;
- and
- one or more memories coupled to the at least one processor and storing programming instructions for execution by the at least one processor to:
- cause an interface to obtain a reordered coded bitstream allocated to a first resource unit (RU) for a first user, the first RU comprises M RUs, and M is a integer greater than 1;
- and
- cause a first tone demapper to restore a sequence of bits in the reordered coded bitstream, wherein a number of data subcarriers (NSD) of the first tone demapper is a positive integer within [NSD_min/Q, NSD_max/Q], wherein NSD_min is a sum of data subcarriers comprised in the first RU, NSD_max is a sum of subcarriers comprised in the first RU, and Q is a number of data subcarriers to which a bit is mapped.
Dependencies are inferred from the claim text.