Memory system and method for controlling memory system

A memory controller connected to a non-volatile memory that stores data encoded with an error correction code that corrects errors of t bits or less, where t is an integer of 2 or more, the memory controller comprising:

• a control circuit;
• a memory interface circuit connected to the non-volatile memory and configured to perform write processing to the non-volatile memory and read processing from the non-volatile memory based on instructions from the control circuit;
• and
• an encoding/decoding circuit that includes a decoding circuit that is configured to perform an error correction on the word read by the memory interface circuit, wherein the decoding circuit is further configured to:
• calculate syndromes using a word read from the non-volatile memory,
• perform a first calculation in which first error locator polynomials from the first order to the k-th order, where k is an integer satisfying 1≤k<t, first error locator polynomials each having an order with the same parity as k, is calculated using the syndromes,
• determine whether or not an error positions are calculable using the first error locator polynomial,
• when it is determined that the error positions are calculable using the first error locator polynomial, calculate the error positions using the first error locator polynomial,
• when it is determined that the error positions are not calculable using the first error locator polynomial, calculate an initial value of a parameter used in a second calculation in which a second error locator polynomials up to the t-th order is calculated using the first error locator polynomials, perform the second calculation using the initial value, and calculate the error positions using the second error locator polynomial, and
• correct an error of the word at either the error positions calculated using the first error locator polynomial or the error positions calculated using the second error locator polynomial.

A method for controlling a memory system comprising a non-volatile memory that stores data encoded with an error correction code that corrects errors of t bits or less, where t is an integer of 2 or more, and a memory controller configured to control writing to the non-volatile memory and reading from the non-volatile memory, the method comprising:

• calculating syndromes using a word read from the non-volatile memory;
• performing a first calculation in which among first error locator polynomials from the first order to the k-th order, where k is an integer satisfying 1≤k<t, first error locator polynomials each having an order with the same parity as k, is calculated using the syndromes;
• determining whether or not an error positions are calculable using the first error locator polynomial;
• when it is determined that the error positions are calculable using the first error locator polynomial, calculating the error positions using the first error locator polynomial;
• when it is determined that the error positions are not calculable using the first error locator polynomial, calculating an initial value of a parameter used in a second calculation in which a second error locator polynomials up to the t-th order is calculated using the first error locator polynomials, performing the second calculation using the initial value, and calculating the error positions using the second error locator polynomial calculated in the second calculation;
• and
• correcting an error of the received word at either the error positions calculated using the first error locator polynomial or the error positions calculated using the second error locator polynomial.