Sampling system with settling error cancellation

A sampling system comprising:

• a sampler circuit, coupled between an input port and an output port of the sampling system, wherein the sampler circuit comprises at least one sampling capacitor;
• a first settling error canceller circuit, coupled between the input port and the output port of the sampling system, wherein the first settling error canceller circuit comprises at least one first sampling capacitor;
• and
• a second settling error canceller circuit, coupled between the input port and the output port of the sampling system, wherein the second settling error canceller circuit comprises at least one second sampling capacitor;
• wherein during a first phase of a settling error cancellation operation, the sampler circuit is arranged to sample a voltage input derived from the input port at the at least one sampling capacitor, the first settling error canceller circuit is arranged to sample the voltage input derived from the input port at the at least one first sampling capacitor, and the second settling error canceller circuit is arranged to hold its sampling result at the at least one second sampling capacitor;
• during a second phase of the settling error cancellation operation that is a next phase of the first phase, the sampler circuit and the second settling error canceller circuit are arranged to perform charge redistribution between the at least one sampling capacitor and the at least one second sampling capacitor, and the first settling error canceller circuit is arranged to hold its sampling result at the at least one first sampling capacitor;
• during a third phase of the settling error cancellation operation that is a next phase of the second phase, the sampler circuit is arranged to sample the voltage input derived from the input port at the at least one sampling capacitor, the second settling error canceller circuit is arranged to sample the voltage input derived from the input port at the at least one second sampling capacitor, and the first settling error canceller circuit is arranged to hold its sampling result at the at least one first sampling capacitor;
• and
• during a fourth phase of the settling error cancellation operation that is a next phase of the third phase, the sampler circuit and the first settling error canceller circuit are arranged to perform charge redistribution between the at least one sampling capacitor and the at least one first sampling capacitor, and the second settling error canceller circuit is arranged to hold its sampling result at the at least one second sampling capacitor.