Phase-Locked Loop (PLL) Circuitry having Phase Interpolators with Reduced Power Consumption

A method of operating phase-locked loop circuitry, comprising:

• with an oscillator, producing an output clock signal;
• with a frequency divider, receiving the output clock signal and outputting a plurality of clock signals;
• with a multiplexer, receiving the plurality of clock signals and selectively outputting first and second clock signals from among the plurality of clock signals;
• with a phase interpolator, receiving the first and second clock signals and outputting a feedback clock signal;
• and
• with a time-to-digital converter, receiving the first clock signal from the multiplexer and the feedback clock signal from the phase interpolator.

A phase interpolator circuit comprising:

• a first input configured to receive a first clock signal;
• a second input configured to receive a second clock signal different than the first clock signal;
• and
• a plurality of delay cells forming a first digital-to-analog converter (DAC) circuit and a second digital-to-analog converter (DAC) circuit separate from the first DAC circuit, wherein:
• the first DAC circuit is controlled using a first coding scheme;
• and
• the second DAC circuit is controlled using a second coding scheme different than the first coding scheme.