Power gating circuit and semiconductor apparatus including the power gating circuit
AssigneeSK hynix Inc.
InventorYun Suk HONG
Life of this patent
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Abstract
A power gating circuit includes a power gating switch and a switching circuit. The power gating switch is coupled to a function block and operates in response to a voltage level of a first node. The switching circuit turns off the power gating switch by discharging the first node to a second driving voltage level during a first time period after blocking a first driving voltage from being applied to the first node in accordance with a plurality of control signals, and applying a third driving voltage to the first node during a second time period after the first time period.
Claims21
A power gating circuit, comprising:
- a power gating switch configured to be coupled to a function block and configured to operate in response to a voltage level of a first node;
- and
- a switching circuit configured to turn off the power gating switch by:
- discharging the first node to a second driving voltage level during a first time period after blocking a first driving voltage from being applied to the first node in accordance with a plurality of control signals;
- and
- applying a third driving voltage to the first node during a second time period after the first time period.
A power gating circuit, comprising:
- a power gating switch configured to be coupled to a function block and configured to operate in response to a voltage level of a first node;
- a first transistor configured to receive a first driving voltage at its source terminal, couple its drain terminal to the first node, and operate according to a first control signal;
- a second transistor configured to receive a second driving voltage at its source terminal, couple its drain terminal to the first node, and operate according to a second control signal;
- and
- a third transistor configured to receive a third driving voltage at its source terminal, couple its drain terminal to the drain terminal of the first transistor, and operate according to a third control signal.
A semiconductor apparatus, comprising:
- a plurality of memory banks;
- a plurality of column driving regions configured to be coupled to the plurality of memory banks, configured to receive a first driving voltage and a third driving voltage, and configured to include circuits associated with column operations of each of the plurality of memory banks;
- and
- a voltage generation circuit configured to generate the third driving voltage in response to a power source that is external to the semiconductor apparatus, and configured to provide the third driving voltage to each of the plurality of column driving regions,
- wherein each of the plurality of column driving regions includes at least one function block and a power gating circuit coupled to the function block, and
- wherein the power gating circuit includes:
- a power gating switch configured to be coupled to the function block and configured to operate in response to a voltage level of a first node;
- and a switching circuit configured to turn off the power gating switch by:
- discharging the first node to a second driving voltage level during a first time period after blocking the first driving voltage from being applied to the first node in accordance with a plurality of control signals;
- and
- applying the third driving voltage to the first node during a second time period after the first time period.
Dependencies are inferred from the claim text.