Power amplification device

A power amplification device, comprising:

• a substrate;
• a first integrated circuit on a major surface of the substrate;
• a second integrated circuit that is at a position different from the first integrated circuit on the major surface of the substrate and is coupled to the first integrated circuit via a plurality of wires provided in or on the substrate;
• a splitter;
• a carrier amplifier comprising a first-stage carrier amplifier configured to amplify an inputted high-frequency signal and a final-stage carrier amplifier configured to amplify a high-frequency signal outputted from the first-stage carrier amplifier;
• a peak amplifier comprising a first-stage peak amplifier configured to amplify the inputted high-frequency signal and a final-stage peak amplifier configured to amplify a high-frequency signal outputted from the first-stage peak amplifier;
• a first bias circuit configured to provide bias to the carrier amplifier;
• a second bias circuit configured to provide bias to the peak amplifier;
• a drive-level detector (DLD) circuit configured to output a signal indicating a drive level of the carrier amplifier, based on a high-frequency signal outputted by the first bias circuit;
• a control circuit;
• and
• a coupler on the major surface of the substrate,
• wherein the first integrated circuit comprises the splitter, the first-stage carrier amplifier, the first-stage peak amplifier, and the control circuit,
• wherein the second integrated circuit comprises the final-stage carrier amplifier and the final-stage peak amplifier,
• wherein the control circuit comprises:
• a detector circuit configured to output a control signal configured to control the second bias circuit or the peak amplifier, and
• a variable attenuator configured to output to the detector circuit, based on the high-frequency signal inputted to the carrier amplifier and the signal indicating the drive level of the carrier amplifier, a high-frequency signal obtained by attenuating the inputted high-frequency signal, and
• wherein one of the plurality of wires is a DLD coupling wire that is coupled to the drive-level detector circuit.