Memory device, testing method of memory device, and manufacturing method of memory device

A memory device comprising:

• a first chip;
• a second chip stacked above the first chip, the second chip including a substrate, a memory cell array configured to store data in a non-volatile manner, a first via, a second via, and a third via, each of the first to third vias passing through the substrate in a stacking direction and being connected to the first chip;
• and
• a switching circuit configured to switch among:
• a first state in which, between the first chip and the second chip, a first signal is communicated through the first via and a second signal is communicated through the second via;
• a second state in which, between the first chip and the second chip, the first signal is communicated through the third via and the second signal is communicated through the second via;
• and
• a third state in which, between the first chip and the second chip, the first signal is communicated through the first via and the second signal is communicated through the third via.