Memory device and memory system

A memory device comprising:

• a string of memory cells coupled in series with each other;
• a bit line coupled to an end of the string of memory cells;
• a plurality of word lines respectively coupled to the string of memory cells;
• a source line coupled to another end of the string of memory cells;
• and
• a controller configured to execute a first read operation including a first read sequence and a second read sequence,
• wherein the controller is configured to:
• in the first read sequence, search for a read voltage,
• in the second read sequence,
• execute a read operation, based on the searched read voltage,
• while a first read voltage is applied to a selected word line of the plurality of word lines, execute a plurality of times of read on the string of memory cells, each of the times of read resulting in a corresponding bit count, and
• while the first read voltage is applied to the selected word line of the plurality of word lines, execute another read based on the result of the bit count of each of the times of read.

A memory device comprising:

• a string of memory cells coupled in series with each other;
• a bit line coupled to one end of the string of memory cells;
• a plurality of word lines respectively coupled to the string of memory cells;
• a source line coupled to another end of the string of memory cells;
• and
• a controller coupled to the string of memory cells, the controller configured to:
• increase, during a first time period, a voltage commonly applied to the word lines,
• apply, during a second time period, a first read voltage to a word line coupled to a target memory cell of the string of memory cells to read data stored by the target memory cell, the first read voltage obtained based on the voltage commonly applied to the word lines, and
• apply, during the second time period, a second voltage to the remaining word lines coupled to the other memory cells of the string of memory cells.