Gate induced drain leakage erase with adaptive bias on top drainside select gate transistor and bottom source-side select gate transistor

A controller in communication with a memory apparatus including drain-side select gate transistors for coupling to a drain-side of each of a plurality of memory holes of memory cells and configured to retain a drain-side transistor threshold voltage, the memory apparatus including source-side select gate transistors for coupling to a source-side of each of the plurality of the plurality of the memory holes of the memory cells and configured to retain a source-side transistor threshold voltage, the controller configured to:

• instruct the memory apparatus to pre-read the drain-side transistor threshold voltage of the drain-side select gate transistors and the source-side transistor threshold voltage of source-side select gate transistors of the plurality of the memory holes having the memory cells being erased in an erase operation;
• and
• instruct the memory apparatus to adjust at least one of a drain-side select gate voltage applied to the drain-side select gate transistors and a source-side select gate voltage applied to the source-side select gate transistors of the plurality of the memory holes having the memory cells being erased during the erase operation based on at least one of the pre-read of the drain-side transistor threshold voltage and the source-side transistor threshold voltage.

A method of operating a memory apparatus including drain-side select gate transistors for coupling to a drain-side of each of a plurality of memory holes of memory cells and configured to retain a drain-side transistor threshold voltage, the memory apparatus including source-side select gate transistors for coupling to a source-side of each of the plurality of the plurality of the memory holes of the memory cells and configured to retain a source-side transistor threshold voltage, the method comprising the steps of:

• pre-reading the drain-side transistor threshold voltage of the drain-side select gate transistors and the source-side transistor threshold voltage of source-side select gate transistors of the plurality of the memory holes having the memory cells being erased in an erase operation;
• and
• adjusting at least one of a drain-side select gate voltage applied to the drain-side select gate transistors and a source-side select gate voltage applied to the source-side select gate transistors of the plurality of the memory holes having the memory cells being erased during the erase operation based on at least one of the pre-read of the drain-side transistor threshold voltage and the source-side transistor threshold voltage.