Gate driving circuit, and display panel and display device including the gate driving circuit

A display panel comprising:

• a display area in which data lines, gate lines, power lines, and sub-pixels are arranged;
• and
• gate drivers configured to supply gate signals to the gate lines,
• wherein at least one of the gate drivers includes:
• a first switching transistor connected between a first gate line and an output node of a first signal transmitter from which a first gate signal is output;
• a second switching transistor connected to the output node of the first signal transmitter;
• a first diode connected between the second switching transistor and the first gate line;
• a third switching transistor connected between a second gate line and an output node of a second signal transmitter from which a second gate signal is output;
• a fourth switching transistor connected to the output node of the second signal transmitter;
• and
• a second diode connected between the fourth switching transistor and the second gate line.

A display device comprising:

• a display panel including a display area in which data lines, gate lines, power lines, and sub-pixels are arranged;
• gate drivers supplying gate signals to the gate lines;
• and
• a data driver connected to the data lines,
• wherein the display area includes at least first and second pixel areas having different refresh rates,
• wherein the sub-pixels of the first pixel area are driven at a first refresh rate, while the sub-pixels of the second pixel area are driven at a second refresh rate that is lower than the first refresh rate, and
• wherein at least one of the gate drivers includes:
• a first switching transistor connected between a first gate line and an output node of a first signal transmitter from which a first gate signal is output;
• a second switching transistor connected to the output node of the first signal transmitter;
• a first diode connected between the second switching transistor and the first gate line;
• a third switching transistor connected between a second gate line and an output node of the second signal transmitter from which a second gate signal is output;
• a fourth switching transistor connected to the output node of the second signal transmitter;
• and
• a second diode connected between the fourth switching transistor and the second gate line.