Shift register, and gate drive circuit and driving method therefor

A gate drive circuit, comprising:

• a plurality of stages of cascaded shift registers comprising:
• a first control module, a second control module, and an output module, wherein an output terminal of the first control module is connected to a first node, and an output terminal of the second control module is connected to a second node;
• the first control module is configured to control, based on a signal of a first clock signal terminal, a signal of a second clock signal terminal, and a level of the second node, an initial signal and a first level signal to be transmitted to the first node;
• the second control module is configured to control, based on the initial signal and a signal of a third clock signal terminal, a second level signal and the signal of the third clock signal terminal to be transmitted to the second node;
• and
• the output module is configured to control, based on a level of the first node, the signal of the second clock signal terminal to be transmitted to an output terminal of the shift register, and control, based on the level of the second node, the first level signal to be transmitted to the output terminal of the shift register, wherein
• an effective level pulse of the second clock signal terminal is delayed relative to an effective level pulse of the first clock signal terminal, and a delay time is greater than or equal to ½ of a time corresponding to the effective level pulse;
• an effective level pulse of the third clock signal terminal is delayed relative to the effective level pulse of the second clock signal terminal;
• and an effective level pulse of the initial signal overlaps with an effective level pulse of the signal of the first clock signal terminal, wherein
• the gate drive circuit further comprises:
• a first clock signal line, a second clock signal line, a third clock signal line, and a fourth clock signal line, wherein the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line are configured to transmit clock signals whose timings are sequentially delayed;
• a first clock signal terminal of a (4n-3)th stage of shift register is connected to the first clock signal line, a second clock signal terminal of the (4n-3)th stage of shift register is connected to the second clock signal line, and a third clock signal terminal of the (4n-3)th stage of shift register is connected to the fourth clock signal line;
• a first clock signal terminal of a (4n-2)th stage of shift register is connected to the second clock signal line, a second clock signal terminal of the (4n-2)th stage of shift register is connected to the third clock signal line, and a third clock signal terminal of the (4n-2)th stage of shift register is connected to the first clock signal line;
• a first clock signal terminal of a (4n-1)th stage of shift register is connected to the third clock signal line, a second clock signal terminal of the (4n-1)th stage of shift register is connected to the fourth clock signal line, and a third clock signal terminal of the (4n-1)th stage of shift register is connected to the second clock signal line;
• a first clock signal terminal of a 4nth stage of shift register is connected to the fourth clock signal line, a second clock signal terminal of the 4nth stage of shift register is connected to the first clock signal line, and a third clock signal terminal of the 4nth stage of shift register is connected to the third clock signal line, wherein
• n is an integer greater than or equal to 1, and 4n is less than or equal to a total number of shift registers;
• and
• the first clock signal line, the second clock signal line, the third clock signal line, and the fourth clock signal line are configured to transmit clock signals whose timings are sequentially delayed by a preset duration, wherein the preset duration is greater than or equal to ½ of a duration corresponding to an effective level pulse of the clock signal.

A driving method for a gate drive circuit, comprising:

• inputting an initial signal to a first control module, and inputting corresponding signals to a first clock signal terminal and a second clock signal terminal, wherein the first control module controls, based on the signal of the first clock signal terminal, the signal of the second clock signal terminal, and a level of a second node, the initial signal and a first level signal to be transmitted to a first node;
• inputting the initial signal to a second control module, and inputting a corresponding signal to a third clock signal terminal, wherein the second control module controls, based on the initial signal and the signal of the third clock signal terminal, a second level signal and the signal of the third clock signal terminal to be transmitted to the second node;
• and
• controlling, by an output module based on a level of the first node, the signal of the second clock signal terminal to be transmitted to an output terminal of the shift register, and controlling, based on the level of the second node, the first level signal to be transmitted to the output terminal of the shift register, wherein
• an effective level pulse of the second clock signal terminal is delayed relative to an effective level pulse of the first clock signal terminal, and a delay time is greater than or equal to ½ of a time corresponding to the effective level pulse;
• an effective level pulse of the third clock signal terminal is delayed relative to the effective level pulse of the second clock signal terminal;
• and an effective level pulse of the initial signal overlaps with an effective level pulse of the signal of the first clock signal terminal.