Artificial-intelligence-enhanced bias response protocols

A computer-implemented bias response method comprising:

• invoking first transistor-based circuitry configured to calculate using one or more processors a first estimated net consequence (ENC) of a first plan based on a machine learning module trained using numerous records of actions and their corresponding actual net consequences (ANCs);
• invoking second transistor-based circuitry configured to perform a data-driven comparison using the one or more processors of the first plan on behalf of a first user against a first bias filter and thereby to trigger a first evaluation whether or not the first plan has any recognized bias;
• invoking third transistor-based circuitry configured to obtain a first artificial-intelligence-indicated (AII) bias pattern conditionally, partly based on a first actual net consequence of the first plan being unfavorable and partly based on the first evaluation whether or not the first plan has any recognized bias pattern resulting in a determination that the first plan has no recognized bias;
• invoking fourth transistor-based circuitry configured to obtain an updated bias filter by adding the first AII bias pattern to the first bias filter;
• invoking fifth transistor-based circuitry configured to calculate a comparison of a second plan on behalf of the first user against the updated bias filter and to trigger conditionally a determination that the second plan has one or more recognized biases;
• and
• invoking sixth transistor-based circuitry configured to save the determination that the second plan has one or more recognized biases in non-transitory computer-readable storage media.

A computer-implemented bias response system comprising:

• first transistor-based circuitry configured to calculate using one or more processors a first estimated net consequence (ENC) of a first plan based on a machine learning module trained using numerous records of actions and their corresponding actual net consequences (ANCs);
• second transistor-based circuitry configured to perform a data-driven comparison using the one or more processors of the first plan on behalf of a first user against a first bias filter and thereby to trigger a first evaluation whether or not the first plan has any recognized bias;
• third transistor-based circuitry configured to obtain a first artificial-intelligence-indicated (AII) bias pattern conditionally, partly based on a first actual net consequence of the first plan being unfavorable and partly based on the first evaluation whether or not the first plan has any recognized bias pattern resulting in a determination that the first plan has no recognized bias;
• fourth transistor-based circuitry configured to obtain an updated bias filter by adding the first AII bias pattern to the first bias filter;
• fifth transistor-based circuitry configured to calculate a comparison of a second plan on behalf of the first user against the updated bias filter and to trigger conditionally a determination that the second plan has one or more recognized biases;
• and
• sixth transistor-based circuitry configured to save the determination that the second plan has one or more recognized biases in non-transitory computer-readable storage media.