US 2026/0073205 A1Published application

Neural processors supporting winograd convolutions

AssigneeApple Inc.

InventorsLei WANG, Ji Liang Song, Ming Chak J. Ko

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Abstract

Embodiments relate to a neural processor circuit including an input transformation circuit and a neural engine circuit including a kernel transformation circuit configured to generate a number of intermediate kernel parameters. The input transformation circuit can generate, at a first time instance, a first set of intermediate input parameters corresponding to a first subsequence of input parameters for a first pair of convolutions based on the number of intermediate kernel parameters; generate, at the first time instance, a second set of intermediate input parameters corresponding to a second subsequence of input parameters for a second pair of convolutions based on the number of intermediate kernel parameters; and generate, at a second time instance after the first time instance, a third set of intermediate input parameters corresponding to a third subsequence of input parameters for a third pair of convolutions based on the number of intermediate kernel parameters.

Claims20

Dependent claims

A neural processor circuit, comprising:

an input transformation circuit configured to:
generate, at a first time instance, a first set of intermediate input parameters corresponding to a first subsequence of input parameters for a first pair of convolutions;
generate, at the first time instance, a second set of intermediate input parameters corresponding to a second subsequence of input parameters for a second pair of convolutions;
and
generate, at a second time instance after the first time instance, a third set of intermediate input parameters corresponding to a third subsequence of input parameters for a third pair of convolutions, wherein the first pair of convolutions, the second pair of convolutions, and the third pair of convolutions are based on a number of convolutional kernel parameters;
and
a neural engine circuit coupled to the input transformation circuit and comprising a kernel transformation circuit configured to generate a number of intermediate kernel parameters based on the number of convolutional kernel parameters;
wherein the first pair of convolutions are based on the first set of intermediate input parameters and the number of intermediate kernel parameters, the second pair of convolutions are based on the second set of intermediate input parameters and the number of intermediate kernel parameters, and the third pair of convolutions are based on the third set of intermediate input parameters and the number of intermediate kernel parameters.

5 more elements

A method performed by a neural processor circuit, comprising:

generating, by an input transformation circuit, a first set of intermediate input parameters corresponding to a first subsequence of input parameters for a first pair of convolutions;
generating, by the input transformation circuit, a second set of intermediate input parameters corresponding to a second subsequence of input parameters for a second pair of convolutions;
generating, by the input transformation circuit, a third set of intermediate input parameters corresponding to a third subsequence of input parameters for a third pair of convolutions, wherein the first pair of convolutions, the second pair of convolutions, and the third pair of convolutions are based on a number of convolutional kernel parameters;
generating, by a kernel transformation circuit, a number of intermediate kernel parameters, wherein the number of intermediate kernel parameters is larger than a number of convolutional kernel parameters;
generating, by a first pair of accumulators, a first pair of convolution values for the first pair of convolutions at a first time instance based on the number of intermediate kernel parameters;
generating, by the first pair of accumulators, a third pair of convolution values for the third pair of convolutions at a second time instance based on the number of intermediate kernel parameters;
and
generating, by a second pair of accumulators, a second pair of convolution values for the second pair of convolutions at the first time instance based on the number of intermediate kernel parameters.

5 more elements

A neural processor circuit, comprising:

an input transformation circuit configured to:
generate, at a first time instance, a first subset of a first set of intermediate input parameters corresponding to a first subsequence of input parameters for a first pair of convolutions, and a first subset of a second set of intermediate input parameters corresponding to a second subsequence of input parameters for a second pair of convolutions;
generate, at a second time instance, a second subset of the first set of intermediate input parameters, and a second subset of the second set of intermediate input parameters, wherein the first pair of convolutions and the second pair of convolutions are based on a number of convolutional kernel parameters;
a neural engine circuit coupled to the input transformation circuit and comprising:
a kernel transformation circuit configured to generate at the first time instance a first subset of a set of intermediate kernel parameters based on the number of convolutional kernel parameters and to generate at the second time instance a second subset of the set of intermediate kernel parameters;
a first accumulator coupled to the kernel transformation circuit and configured to generate a first set of partial results of a first pair of convolution values for the first pair of convolutions and a first set of partial results of a second pair of convolution values for the second pair of convolutions;
and
a second accumulator coupled to the kernel transformation circuit and configured to generate a second set of partial results of the first pair of convolution values, and a second set of partial results of the second pair of convolution values.

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Dependencies are inferred from the claim text.