Verification method, verification apparatus, and non-transitory computer readable medium
AssigneeKioxia Corporation
InventorYohei KANEMURA
Life of this patent
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Abstract
A verification method for an integrated circuit according to an embodiment includes: acquiring circuit operation information of an integrated circuit to be verified by a logic simulation; and analyzing the circuit operation information and extracting a verification set. The verification method according to the embodiment further includes verifying a logical operation of a location where clock domains are crossed for the verification set for each inter-flip-flop.
Claims15
A verification method for an integrated circuit comprising:
- acquiring circuit operation information of an integrated circuit to be verified by a logic simulation;
- analyzing the circuit operation information and extracting a verification set;
- and
- verifying a logical operation of a location where clock domains are crossed for the verification set for each inter-flip-flop.
A verification apparatus for an integrated circuit comprising:
- an observation point specifying unit configured to specify a point to be observed by a logic simulation from circuit data and timing constraint;
- a logic simulation performing unit configured to observe a state of the specified point by the logic simulation;
- a verification set extraction unit configured to extract a verification set of the point from a result of the logic simulation;
- a CDC verification performing unit configured to verify a logical operation of a location where clock domains are crossed for the verification set for each inter-flip-flop.
A non-transitory computer readable medium used for a verification apparatus for an integrated circuit, the non-transitory computer readable medium storing a program for causing a computer to perform:
- specifying a point to be observed by a logic simulation from circuit data and timing constraint;
- observing a state of the specified point by the logic simulation;
- extracting a verification set of the point from a result of the logic simulation;
- and
- verifying a logical operation of a location where clock domains are crossed for a verification set for each inter-flip-flop.
Dependencies are inferred from the claim text.