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AssigneeIntel Corporation
InventorsHussein ALAMEER, Saravanan SETHURAMAN, James A. MCCALL, Rajat AGARWAL, Xiang LI
Estimating the term…
Disclosed herein is memory device that includes a printed circuit board (PCB) and a plurality of dynamic random-access memory (DRAM) devices arranged on the PCB and logically divided into four pseudo-channels. A shared command/address (C/A) bus of the device is configured to transmit command signals to all four pseudo-channels and a set of multiplexers on the device are controllable to selectively couple data signals between the four pseudo-channels and a memory controller. A control interface of the device is configured to interleave data burst transactions of the data signals across the four pseudo-channels, wherein a burst of the data burst transactions is distributed across two groups, each group comprising two of the four pseudo-channels operating in parallel.
A device comprising:
The device of claim 210, wherein each LPDDR device comprises 8 bits, wherein the five LPDDR devices together provide a 40-bit data width for the data signals.
The non-transitory computer-readable medium of claim 13, wherein each pseudo-channel comprises five 8 bit DRAM devices operating in byte mode.
The non-transitory computer-readable medium of claim 13, further comprising operating the plurality of DRAM devices in byte mode.
The non-transitory computer-readable medium of claim 13, wherein a burst length of the data signals is sixteen, where each group of the two groups handles eight consecutive beats of the burst.
The non-transitory computer-readable medium of claim 13, wherein the shared command/address bus is seven bits wide and time-multiplexed among the pseudo-channels.
A non-transitory computer-readable medium comprising instructions, that, when executed by one or more processors, cause the one or more processors to:
The non-transitory computer-readable medium of claim 13, further comprising operating the DRAM devices at one-fourth of a full data rate of the data signals.
A method comprising:
The method of claim 19, the method further comprising dynamically selecting one of the two groups of pseudo-channels for interleaved access during a first portion of a burst, the method further comprising dynamically selecting the other of the two groups during a second portion of the burst.
Dependencies are inferred from the claim text.