Shadow logic on output, at speed test (memory bypass) architecture for memories without input data

A method of operating a memory circuit, comprising:

• receiving input data at an input latch within a control circuit;
• in a normal operation mode:
• using the input data to access a memory array;
• providing output data from the accessed memory array to a multiplexer via an output circuit;
• passing the output data from the multiplexer to an output latch;
• and
• clocking the output latch with an output from a dummy output circuit of a self timing circuit;
• in a bypass mode:
• activating a bypass mode signal from the control circuit;
• passing the input data from the input latch to the output latch via the multiplexer, bypassing the memory array;
• and
• clocking the output latch with the output from the dummy output circuit of the self-timing circuit;
• and
• processing data from the output latch with an output shadow logic.

A memory circuit, comprising:

• a memory array configured to store data;
• output circuitry coupled to the memory array and configured to output data from the memory array;
• shadow logic circuitry coupled to the output circuitry and configured to perform combinatorial logic operations on data received from the output circuitry;
• bypass circuitry configured to selectively bypass the memory array and provide test data directly to the shadow logic circuitry;
• and
• self-timing circuitry configured to control timing of data propagation through the bypass circuitry using the same timing mechanisms used for normal memory operations.