Memory device capable of selectively interrupting power supply to circuit performing single operation

A memory device comprising:

• a power source line;
• a ground source line;
• a column decoder connected to a plurality of bit lines connected to memory cells and including column selection line drivers configured to select a bit line corresponding to decoded column addresses, the column selection line drivers each including a first driver circuit and a second driver circuit each configured to be driven by a power supply voltage supplied to a first power supply voltage line and a ground voltage supplied to a first ground voltage line, the first driver circuit and the second driver circuit configured to be activated in response to a first most significant bit (MSB) signal corresponding to an MSB signal among the decoded column addresses obtained by excluding decoded column addresses addressing the column selection line drivers;
• and
• a power gating switch circuit configured to connect the power source line and the ground source line to the first power supply voltage line and the first ground voltage line, respectively, of the first driver circuit in response to a first control signal and configured to connect the power source line and the ground source line to the first power supply voltage line and the first ground voltage line, respectively, of the second driver circuit in response to a second control signal.

A memory device comprising:

• first and second power source lines;
• first and second ground source lines;
• a row decoder connected to a plurality of word lines connected to memory cells and including word line driver circuits configured to select a word line corresponding to decoded row addresses, the word line driver circuits being configured to be driven by a power supply voltage supplied to a first power supply voltage line and a ground voltage supplied to a first ground voltage line, and the word line driver circuits being divided, based on a first most significant bit (MSB) signal, into a first group and a second group, the first MSB signal corresponding to an MSB signal among the decoded row addresses;
• a column decoder connected to a plurality of bit lines connected to the memory cells and including column selection line drivers selecting a bit line corresponding to decoded column addresses, the column selection line drivers each including a first driver circuit and a second driver circuit each configured to be driven by the power supply voltage supplied to a second power supply voltage line and the ground voltage supplied to a second ground voltage line, the first driver circuit and the second driver circuit being activated based on a second MSB signal corresponding to an MSB signal among the decoded column addresses obtained by excluding decoded column addresses addressing the column selection line drivers;
• and
• a power gating switch circuit configured to connect the first power source line and the first ground source line to the first power supply voltage line and the first ground voltage line, respectively, of the word line driver circuits in the first group in response to a first control signal, configured to connect the first power source line and the first ground source line to the first power supply voltage line and the first ground voltage line, respectively, of the word line driver circuits in the second group in response to a second control signal, configured to connect the second power source line and the second ground source line to the second power supply voltage line and the second ground voltage line, respectively, of the first driver circuit in response to a third control signal, and configured to connect the second power source line and the second ground source line to the second power supply voltage line and the second ground voltage line, respectively, of the second driver circuit in response to a fourth control signal.