Method and apparatus for fma computation with high linearity and high computational efficiency based on mram-sram cell

A method for performing computation in a computation apparatus comprising a plurality of nvSRAM cells, wherein each nvSRAM cell comprises a first partial cell, and the first partial cell comprises a differential circuit including a first inverter and a second inverter connected in parallel between a power supply voltage and a ground voltage, a first output node of the first inverter being connected to a second input node of the second inverter and a second output node of the second inverter being connected to a first input node of the first inverter;

• a first access transistor having a drain connected to the first output node;
• a second access transistor having a drain connected to the second output node;
• a first MRAM cell including a first selection transistor and a first magnetic tunnel junction connected in series between a CBL node and the first output node;
• and a second MRAM cell including a second selection transistor and a second magnetic tunnel junction connected in series between the CBL node and the second output node, the method comprising:
• a first process of controlling current to flow through each of the plurality of nvSRAM cells for artificial intelligence computation;
• and
• a second process of generating the artificial intelligence computation result according to the respective currents flowing through the plurality of nvSRAM cells.