Efuse memory

An efuse memory, comprising an efuse cell structure, wherein

• the efuse cell structure comprises a control transistor composed of a MOS transistor and a link structure;
• the MOS transistor is formed in a first active area;
• the link structure is formed in a second active area, and the first active area is parallel to the second active area;
• the link structure comprises a first link connection area, an active area link, and a second link connection area;
• the active area link is located between the first link connection area and the second link connection area;
• the top of the first link connection area is connected to a drain line of the MOS transistor through a contact;
• the top of the second link connection area is connected to a bit line through the contact;
• the active area link comprises on and off states;
• when the efuse cell structure is in an initial state, the active area link is in the on state, and the drain and the bit line are electrically connected together;
• and
• when the efuse cell structure is in a programmed state, the active area link is in a fused state, and the drain and the bit line are electrically disconnected from each other.