Computing-in-memory circuit

A computing in memory circuit, comprising:

• a latch, having a word line, a bit line, a complementary bit line, a first output end, and a second output end;
• and
• a first logic circuit, having a first input end, a second input end, and an output end, wherein the output end is coupled to the word line of the latch, the first input end receives a control signal, and the second input end is coupled to a power supply voltage of the latch,
• wherein the complementary bit line of the latch is coupled to a reference voltage,
• the power supply voltage is ramped up from a low level to a high level during an operation of the latch.

A computing-in-memory circuit, comprising:

• a plurality of latches, each of the plurality of latches having a word line, a bit line, a complementary bit line, a first output end, and a second output end, wherein the bit line of each of the plurality of latches is coupled to a local bit line of a corresponding memory string among a plurality of memory strings in a memory array, wherein the corresponding memory string comprises a plurality of storage units, and each of the plurality of storage units consists of a single memory cell, wherein the second output end of each of the plurality of latches provides a weight signal, sensed by the latch, from the memory cell, and the complementary bit line of the latch is coupled to a reference voltage;
• a plurality of first logic circuits, each of the plurality of first logic circuits having a first input end, a second input end, and an output end, wherein the output end of each of the plurality of first logic circuits is coupled to the word line of a corresponding latch among the plurality of latches, the first input end of each of the plurality of first logic circuits receives a control signal, and the second input end of each of the plurality of first logic circuits is coupled to a power supply voltage of the corresponding latch among the plurality of latches;
• and
• a plurality of second logic circuits, each of the plurality of second logic circuits having a first input end, a second input end, and an output end, wherein the first input end of each of the plurality of second logic circuits is coupled to the second output end of the corresponding latch among the plurality of latches, the second input end of each of the plurality of second logic circuits receives an external input signal, and the output end of each of the plurality of second logic circuits outputs a product of the weight signal and the input signal.