Memory Circuitry and Method Used in Forming Memory Circuitry

Memory circuitry comprising strings of memory cells, comprising:

• a stack comprising vertically-alternating insulative tiers and conductive tiers, channel-material strings of memory cells extending through the insulative tiers and the conductive tiers in a memory-array region;
• the insulative tiers and the conductive tiers extending from the memory-array region into a stair-step region, the stair-step region comprising a cavity comprising a flight of stairs having insulative material atop treads of the stairs, individual of the treads comprising conducting material of one of the conductive tiers;
• conductive vias extending through the insulative material, individual of the conductive vias being directly above and directly against the conducting material of the respective individual tread;
• and
• a lining over sidewalls of the individual conductive vias, the lining comprising at least one of (a) and (b), where,
• (a):
• a silicon oxide having dopant therein at a total atomic concentration of 0.1 to 30 percent;
• the dopant being at least one of C, B, and N;
• and
• (b):
• a silicon nitride having dopant therein at a total atomic concentration of 0.1 to 30 percent;
• the dopant being at least one of C and B.