Countermeasure for drain-side select gate upper tail

A controller in communication with a memory apparatus including drain-side select gate transistors for coupling to a drain-side of each of a plurality of memory holes of memory cells and configured to retain a transistor threshold voltage, the controller configured to:

• instruct the memory apparatus to perform a predetermined quantity of erase operations on the memory cells of at least one block of a die of the memory cells;
• and
• report the die as failing in response to determining the transistor threshold voltage of one or more of the drain-side select gate transistors of the at least one block does not meet a predetermined criteria.

A method of operating a memory apparatus including drain-side select gate transistors for coupling to a drain-side of each of a plurality of memory holes of memory cells and configured to retain a transistor threshold voltage, the method comprising the steps of:

• performing a predetermined quantity of erase operations on the memory cells of at least one block of a die of the memory cells;
• and
• reporting the die as failing in response to determining the transistor threshold voltage of one or more of the drain-side select gate transistors of the at least one block does not meet a predetermined criteria.