Process and temperature compensated word line underdrive scheme for sram

An electronic device, comprising:

• a plurality of row decoders, each row decoder comprising:
• decoder logic configured to generate an initial word line signal;
• word line driver circuitry configured to generate an inverse word line signal at an intermediate node from the initial word line signal, and to generate a word line signal at a word line node from the inverse word line signal;
• and
• a word line underdrive p-channel transistor having a source coupled to the intermediate node, a drain, and a gate controlled based upon the inverse word line signal;
• control circuitry comprising a word line underdrive sink circuit, the word line underdrive sink circuit comprising:
• a first dummy memory cell including:
• a first pass gate transistor having a conduction terminal connected to a first node, with other terminals thereof left floating;
• a second pass gate transistor having a first conduction terminal connected to a second node, a second conduction terminal connected to the drain of the word line underdrive p-channel transistor, and a gate connected to ground;
• a first inverter having an input connected to the second node, an output connected to the first node, and first and second power terminals left floating;
• and
• a second inverter having an input connected to the first node, an output connected to the second node, a first power terminal connected to a voltage supply node, and a second power terminal left floating;
• a second dummy memory cell including:
• a third pass gate transistor having a first conduction terminal connected to a third node, with other terminals thereof left floating;
• a fourth pass gate transistor having a first conduction terminal connected to a fourth node, a second conduction terminal connected to the drain of word line underdrive p-channel transistor, and a gate connected to the voltage supply node;
• a third inverter having an input connected to the fourth node, an output connected to the third node, and first and second power terminals left floating;
• and
• a fourth inverter having an input connected to the third node, an output connected to the fourth node, a first power terminal left floating, and a second power terminal connected to ground;
• wherein the second node and fourth node are connected to a common node, wherein the third node is connected to the voltage supply node, and wherein the first node is connected to receive an inverse of a clock signal.