Memory devices and methods of manufacturing thereof

A memory device, comprising:

• a first memory cell including a first memory transistor serially connected to a first memory resistor, wherein the first memory transistor having a first source/drain terminal, a second source/drain terminal, and a gate terminal;
• a second memory cell including a second memory transistor serially connected to a second memory resistor, wherein the second memory transistor having a first source/drain terminal, a second source/drain terminal, and a gate terminal;
• a first shunt component including a first shunt transistor and a first shunt resistor, wherein the first shunt transistor having a first source/drain terminal, a second source/drain terminal, and a gate terminal;
• and
• a second shunt component including a second shunt transistor and a second shunt resistor, wherein the second shunt transistor having a first source/drain terminal, a second source/drain terminal, and a gate terminal;
• wherein the first source/drain terminal of the first shunt transistor and the first source/drain terminal of the second shunt transistor are electrically coupled to each other, the second source/drain terminal of the first shunt transistor is electrically connected to the first source/drain terminal of the first memory transistor, the second source/drain terminal of the second shunt transistor is electrically connected to the first source/drain terminal of the second memory transistor, and the first source/drain terminal of the first memory transistor and the first source/drain terminal of the second memory transistor are electrically coupled to each other.

A method for forming memory devices, comprising:

• forming a memory array including a plurality of memory transistors arranged over a plurality of rows and a plurality of columns;
• forming an additional row including a plurality of shunt transistors arranged along the plurality of columns, respectively, wherein the plurality of shunt transistors have their first source/drain terminals serially connected to first source/drain terminals of a subset of the plurality of memory transistors that are arranged across the plurality of columns, respectively;
• forming at least one contact structure electrically coupling the first source/drain terminals of the subset of the plurality of memory transistors;
• forming a plurality of first metal tracks along the plurality of columns, respectively, wherein each of the plurality of first metal tracks is electrically coupled to the at least one contact structure;
• forming a second metal track shunting respective second source/drain terminals of the plurality of shunt transistors;
• forming a third metal track electrically coupled to respective gate terminals of the plurality of shunt transistors;
• and
• forming a plurality of memory resistors electrically coupled to second source/drain terminals of the subset of the plurality of memory transistors, respectively.