DETECTION OF STEALTHY BITSTREAMS IN FIELD PROGRAMMABLE GATE ARRAYS (FPGAs)
AssigneeArizona Board of Regents on behalf of Arizona State University
InventorsJayeeta Chaudhuri, Krishnendu Chakrabarty
Life of this patent
Estimating the term…
Abstract
A method of detecting stealthy bitstreams in field programmable gate arrays (FPGAs) includes receiving an FPGA bitstream for configuring an FPGA; converting the FPGA bitstream into images; generating a graph from the images using a similarity evaluation; and performing a classification of the FPGA bitstream as benign or malicious using the graph as input to a graph convolutional network.
Claims20
A method of detecting stealthy bitstreams in field programmable gate arrays (FPGAs), comprising:
- receiving an FPGA bitstream for configuring an FPGA;
- converting the FPGA bitstream into images;
- generating a graph from the images using a similarity evaluation;
- and
- performing a classification of the FPGA bitstream as benign or malicious using the graph as input to a graph convolutional network.
A system for detecting stealthy bitstreams in field programmable gate arrays (FPGAs), comprising:
- a convolutional neural network (CNN);
- a graph convolutional network (GCN);
- a multilayer perceptron (MLP);
- one or more processors;
- memory;
- and
- instructions for detecting stealthy bitstreams in FPGAs stored in the memory that when executed by at least one of the one or more processors direct the system to:
- receive an FPGA bitstream for configuring an FPGA;
- partition the FPGA bitstream into non-overlapping windows;
- input the non-overlapping windows of the FPGA bitstream to the CNN to generate a first feature set;
- convert each bitstream window of the non-overlapping windows of the FPGA bitstream to an image;
- generate a graph from the images using a similarity evaluation;
- generate node embeddings from the graph using the GCN having a feature vector comprising a combination of the first feature set and a second feature set generated from applying a Fast Fourier Transform on each bitstream window;
- and
- perform machine learning inference on the node embeddings using the MLP to classify the FPGA bitstream as benign or malicious.
A computer-readable storage medium storing instructions that when executed cause a system to:
- receive an FPGA bitstream for configuring an FPGA deployed on a shared FPGA infrastructure;
- convert the FPGA bitstream into images;
- generate a graph from the images using a similarity evaluation to analyze spatial relationships between bitstream segments;
- perform a classification of the FPGA bitstream as benign or malicious using the graph as input to a graph convolutional network;
- analyze the FPGA bitstream for dispersed malicious circuits having components distributed across non-contiguous look-up tables based on the classification;
- and
- prevent deployment of the FPGA bitstream on the shared FPGA infrastructure when malicious dispersed circuits are detected.
Dependencies are inferred from the claim text.