Frame delay time counting circuit and near field communication card including the same

A frame delay time (FDT) counting circuit in a near field communication (NFC) card, the FDT counting circuit comprising:

• a first comparator configured to compare an envelope voltage signal with a first reference voltage and output a first comparison output signal;
• a second comparator configured to compare the envelope voltage signal with a second reference voltage and output a second comparison output signal;
• an FDT compensation circuit configured to generate a compensation signal based on the first comparison output signal and the second comparison output signal;
• and
• a trigger generation circuit configured to output a trigger signal based on the first comparison output signal and the compensation signal,
• wherein the trigger signal initiates a transmitting operation of the NFC card.

A near field communication (NFC) system comprising an NFC card,

• wherein the NFC card comprises:
• a rectification and filtering circuit configured to receive a radio signal and generate an envelope voltage signal based on the radio signal, and the envelope voltage signal including a plurality of pause sections;
• and
• a frame delay time (FDT) counting circuit configured to detect a rising section of a last pause section, measure the rising slope of the last pause section, and generate a trigger signal based on the measured value of the rising slope of the last pause section, and the trigger signal triggering a transmitting operation of the NFC card within a frame delay time (FDT) from the rising section of the last pause section,
• wherein the FDT counting circuit comprises:
• a first comparator configured to compare the envelope voltage signal with a first reference voltage and output a first comparison output signal;
• a second comparator configured to compare the envelope voltage signal with a second reference voltage and output a second comparison output signal;
• an FDT compensation circuit configured to output a compensation signal based on the first comparison output signal and the second comparison output signal;
• and
• a trigger generation circuit configured to output the trigger signal based on the first comparison output signal and the compensation signal.