Multiple Chip Versions From Integrated Design Process

An integrated circuit, comprising:

• first circuitry implementing a first component of a system-on-a-chip (SOC), wherein the first component is a modified version of a second component included in a different integrated circuit;
• and
• additional circuitry implementing a first set of additional components forming a least a subset of a second set of additional components included in the different integrated circuit;
• and
• a stored first chip identifier matching a second chip identifier stored by the different integrated circuit.

A method, comprising:

• defining representations of a plurality of components for a first system-on-a-chip (SOC) in a collection of design information, wherein at least a first component of the plurality of components is modified for inclusion in a second SOC that includes at least a subset of the plurality of components, and wherein at least a portion of the collection of design information is parameterized to reflect the first component in the first SOC and the modified first component in the second SOC;
• producing, from the collection of design information using a first configuration of parameters for the at least a portion of the collection of design information, a first netlist for the first SOC;
• producing, from at least a subset of the collection of design information using a second configuration of parameters for the at least a portion of the collection of design information, a second netlist for the second SOC;
• generating, using the first netlist, a first design database representing a first physical arrangement of circuit elements implementing the plurality of components in the first SOC;
• generating, using the second netlist, a second design database representing a second physical arrangement of circuit elements implementing the at least a subset of the plurality of components in the second SOC;
• and
• producing a first fabrication data set for the first SOC based on the first design database and a second fabrication data set for the second SOC based on the second design database, wherein a power domain partitioning from the first SOC is retained in the second SOC.