Atomic updating of page table entry status bits

A computer program product embodied in a non-transitory computer readable medium for instruction execution, the computer program product comprising code which causes one or more processors to generate semiconductor logic for:

• accessing a processor core, wherein the processor core supports virtual memory addressing, and wherein the processor core includes a memory management unit (MMU) and a load store unit (LSU);
• performing, by the MMU, a page table walk, wherein the page table walk is responsive to a memory operation, wherein the page table walk identifies a page table entry (PTE) for a virtual to physical address translation;
• reading the PTE, wherein the reading obtains a first value from the PTE, and wherein the reading includes determining, by the MMU, to update one or more status bits within the PTE;
• re-reading, by the LSU, the PTE, wherein the re-reading obtains a second value from the PTE;
• updating, by the LSU, the PTE, wherein the updating includes the one or more status bits, wherein the updating is based on a match between the first value and the second value;
• and
• storing, in a page table, the PTE that was updated, wherein the re-reading, the updating, and the storing are performed atomically.

A computer system for instruction execution comprising:

• a memory which stores instructions;
• one or more processors coupled to the memory, wherein the one or more processors, when executing the instructions which are stored, are configured to:
• access a processor core, wherein the processor core supports virtual memory addressing, and wherein the processor core includes a memory management unit (MMU) and a load store unit (LSU);
• perform, by the MMU, a page table walk, wherein the page table walk is responsive to a memory operation, wherein the page table walk identifies a page table entry (PTE) for a virtual to physical address translation;
• read the PTE, wherein the reading obtains a first value from the PTE, and wherein the reading includes determining, by the MMU, to update one or more status bits within the PTE;
• re-read, by the LSU, the PTE, wherein the re-reading obtains a second value from the PTE;
• update, by the LSU, the PTE, wherein the updating includes the one or more status bits, wherein the updating is based on a match between the first value and the second value;
• and
• store, in a page table, the PTE that was updated, wherein the re-reading, the updating, and the storing are performed atomically.