Memory allocation in a reconfigurable data processor

A method for a data processing system comprising:

• an array of reconfigurable units including a plurality of pattern compute units (PCUs) and a plurality of pattern memory units (PMUs), each of the plurality of the PMUs further comprising a memory having one or more first type of (read) I/O ports and one or more second type of (write) I/O ports, the method comprising:
• receiving by a compiler, a tensor including ‘n’ read memory access patterns or ‘m’ write memory access patterns located in a logical memory of the compiler, a read memory access pattern (read context) including a read memory access (read data region) and a write memory access pattern (write context) including a write memory access (write data region);
• creating by the compiler, a plurality of copies of the tensor to create a plurality of duplicate tensors;
• and
• assigning by the compiler, up to ‘n’ read contexts or up to ‘m’ write contexts to one or more duplicate tensors, such that no duplicate tensor has more contexts of a particular type than ports of that type.