Optimizing usage of the namespace logical-to-physical reference table in memory devices

A system comprising:

• a first memory device;
• and
• a processing device, operatively coupled with the memory device, to perform operations comprising:
• storing, on a first memory device, a first address translation metadata structure;
• receiving an instruction reflecting a namespace change associated with a zoned namespace;
• updating the first address translation metadata structure based on the instruction;
• updating an address translation metadata pointer to reference the first address translation metadata structure during address translation operations associated with the plurality of zoned namespaces;
• copying the first address translation metadata structure into a second memory device thus creating a second address translation metadata structure;
• and
• updating the hardware register to point to the second address translation metadata structure during address translation operations associated with the plurality of zoned namespaces.

A non-transitory computer-readable medium storing instructions, which when executed by a processing device, cause the processing device to perform operations comprising:

• storing, on a first memory device, a first address translation metadata structure;
• receiving an instruction reflecting a namespace change associated with a zoned namespace;
• updating the first address translation metadata structure based on the instruction;
• updating an address translation metadata pointer to reference the first address translation metadata structure during address translation operations associated with the plurality of zoned namespaces;
• copying the first address translation metadata structure into a second memory device thus creating a second address translation metadata structure;
• and
• updating the hardware register to point to the second address translation metadata structure during address translation operations associated with the plurality of zoned namespaces.