Controller Memory Buffer (CMB) As Cache

A data storage device, comprising:

• a memory device;
• and
• a controller coupled to the memory device, wherein the controller is configured to:
• pre-fetch data from the memory device prior to receiving a read command to read the data from the memory device, wherein the pre-fetched data has a logical block address (LBA);
• store the pre-fetched data in dynamic random access memory (DRAM) at a DRAM address;
• inform a LBA to DRAM (L2D) module of the LBA for the pre-fetched data and the DRAM address;
• receive the read command, wherein the read command is to read the data from the memory device to a controller memory buffer (CMB);
• access the data from the DRAM;
• receive a physical region page (PRP) for the read command;
• and
• send the PRP to the L2D module.

A data storage device, comprising:

• means to store data;
• and
• a controller coupled to the means to store data, wherein the controller is configured to:
• dynamically remap a range from a first portion of the means to store data to a second portion of the means to store data, wherein the second portion of the means to store data is a controller memory buffer (CMB);
• maintain a module to hold lists of logical block address (LBA) to physical region page (PRP) relationships and LBA to the first portion relationships of data that has been pre-fetched;
• receive a read command from a host device, wherein the read command has a logical block address (LBA);
• forward the LBA to a LBA to dynamic random access memory (DRAM) (L2D) module;
• and
• receive a physical region page (PRP) with the read command and send the PRP to the L2D module.