US 2026/0064534 A1 · COORDINATED ERROR CORRECTION

Abstract

Methods, systems, and devices for coordinated error correction are described. A memory device may indicate, for example to an external device, that errors were detected in data that was stored by the memory device and requested by the external device based on a comparison between an error correction code stored when the data was written to a memory array and an error correction code generated when the data is read from the memory array. After performing the comparison, an indication of or based on whether the compared error correction codes match may be provided to the external device. The external device may use the indication to detect errors in the received version of the data, or to manage data storage in the memory device, or both, among other operations.

Claims20

Dependent claims

A method, comprising:

receiving, at a memory device comprising a memory array, a read command from a host device;
reading a set of data from the memory array based at least in part on the read command;
altering, based at least in part on performing an error correction procedure for the set of data, a value of a bit in the set of data to obtain an altered set of data;
and
transmitting, to the host device, the altered set of data and an indication of whether an error was detected in the set of data, wherein the indication comprises a type of the error in the set of data that was corrected by the memory device when the indication signals that an error was detected in the set of data.

2 more elements

An apparatus, comprising:

one or more controllers configured to transmit, to one or more memory devices, a read command to read a set of data from one or more memory arrays of the one or more memory devices;
and
the one or more memory devices comprising the one or more memory arrays, wherein the one or more memory devices are configured to:
receive the read command;
read the set of data from the one or more memory arrays in response to the read command;
generating an altered set of data based at least in part on a value of a bit in the set of data that is modified in accordance with one or more error correction procedures for the set of data;
and
transmit the altered set of data and an indication of whether an error was detected in the set of data, wherein the indication comprises a type of the error in the set of data that was corrected when the indication comprises an indication that the error was detected in the set of data.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application

19/380,806Filed 5 Nov 2025

Priority

13 Aug 2019

Published

5 Mar 2026

Term ends

Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 11/1076
Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's: parity data used in redundant arrays of…
H03M 13/05
Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words:…
G06F 11/1048
In individual solid state devices: using arrangements adapted for a specific error detection or correction feature
H03M 13/2906
Combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes: using…

Family

Application62/885,925Us provisional application · filed 13 Aug 2019

Application16/940,783Continuation · filed 28 Jul 2020

Application17/690,772Continuation · filed 9 Mar 2022

Application18/379,057Continuation · filed 11 Oct 2023

Application19/380,806Continuation

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US 2024/0111627 A1Published application

US 2026/0064534 A1This patent

From the US filing history. Foreign family members aren’t listed.

Coordinated error correction

Life of this patent

Coordinated error correction

Life of this patent

Abstract

Claims20