US 2026/0064530 A1Published application

Memory controller and mcu chip

AssigneeGigadevice Semiconductor Inc.

InventorsYang GAO, Nanfei WANG

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Abstract

A memory controller and an MCU chip are provided by the present application. The memory controller adds a second memory controller to conventional memory controller architecture and is coupled to second NVM storing a backup of content of first NVM in the memory controller. With this arrangement, one more memory access path is established, which takes full advantage of the fast reading characteristics of the first NVM, and once a system bus identifies an error in content read from the first NVM or a problematic address, the second memory controller can automatically read exactly corresponding backup content from the second NVM and provide it on the system bus, or use it to accurately correct the error in the first NVM. This ensures correctness of content that a central processing unit (CPU) or other master on the system bus reads, without interrupting execution of the system's program.

Claims20

Dependent claims

A memory controller, coupled to a second non-volatile memory (NVM) and comprising:

a first NVM having a faster read and write speed than the second NVM and serving as a main memory for storing content necessary for operation of a system;
a first memory controller responsible for a read and write control of the first NVM;
a first bus interface, coupled to each of the first memory controller and a system bus and is configured for transfer of content between the system bus and the first memory controller;
a second memory controller, coupled to the first memory controller and configured to:
cooperate with the first memory controller to back up content in the first NVM to the second NVM;
and according to configuration information, read corresponding backup content from the second NVM and transfer the corresponding backup content to the system bus, or write the corresponding backup content from the second NVM to the first NVM through the first memory controller for content repair.

3 more elements

Dependencies are inferred from the claim text.

Facts

Application: 19/309,721Filed 26 Aug 2025
Priority: CN 202411204204.729 Aug 2024
Published: 5 Mar 2026
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 11/1068
In individual solid state devices: in sector programmable memories, e.g. flash disk
G06F 11/1666
Error detection or correction of the data by redundancy in hardware: where the redundant component is memory or memory area
G06F 11/1016
Using codes or arrangements adapted for a specific type of error: error in accessing a memory location, i.e. addressing error
G06F 11/1441
At system level: resetting or repowering

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