Memory controller and mcu chip
AssigneeGigadevice Semiconductor Inc.
InventorYang GAO
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Abstract
A memory controller (MC) and a microcontroller unit (MCU) chip are disclosed. The MC is obtained by adding a smart load control (SLC) module to an MC architecture with an ECC logic module. When a CPU is reading contents from first memory, the ECC logic module can accurately identify soft failure locations and correct 1, 2 or more bit errors, and when errors exceeding the error correction ability of the ECC logic module, the SLC module can select a suitable error correction mode for handling the soft failures in the first memory based on conditions of different ECC errors and soft failure locations as well as on the system's error correction need.
Claims20
A memory controller, coupled to a central processing unit (CPU), a first memory and a second memory, the first memory being associated with a higher soft-failure probability than the second memory, one of the first memory and the second memory being a main memory and the other one of the first memory and the second memory being configured to back up at least a part of contents in the main memory, wherein the memory controller comprises:
- an error checking and correction (ECC) logic module, configured to, during reading of contents by the CPU from the first memory, perform an ECC on the contents from the first memory to detect and correct error contents from the first memory in real time, wherein in case of errors exceeding an error correction ability, a soft-failure induced ECC error occurs;
- and
- a smart load controller (SLC) module, configured to select different error correction modes for handling the soft failures in the first memory based on conditions of different ECC errors obtained by the ECC logic module and soft failure locations, wherein the handling comprises overwriting and refreshing or invalidating the soft failure locations in the first memory,
- wherein a required address range of said different error correction modes varies in size.
A microcontroller unit (MCU) chip comprising:
- a central processing unit (CPU), a first memory and a memory controller, which are integrated in a single chip package, wherein a second memory is disposed inside or outside the MCU chip and is coupled to the memory controller,
- wherein the first memory is associated with a higher soft-failure probability than the second memory, wherein one of the first memory and the second memory is a main memory and the other one of the first memory and the second memory is configured to back up at least a part of contents in the main memory under control of the memory controller,
- wherein the memory controller comprises:
- an error checking and correction (ECC) logic module, configured to, during reading of contents by the CPU from the first memory, perform an ECC on the contents from the first memory to detect and correct error contents from the first memory in real time, wherein in case of errors exceeding an error correction ability, a soft-failure induced ECC error occurs;
- and
- a smart load controller (SLC) module, configured to select different error correction modes for handling the soft failures in the first memory based on conditions of different ECC errors obtained by the ECC logic module and soft failure locations, wherein the handling comprises overwriting and refreshing or invalidating the soft failure locations in the first memory,
- wherein a required address range of said different error correction modes varies in size.
Dependencies are inferred from the claim text.