US 2026/0064526 A1 · MEMORY DEVICE BAD COLUMN IDENTIFICATION AND COMPENSATION

Abstract

A method for managing error correction in a memory device includes identifying, by a memory controller, codewords in a memory array of the memory device that have bad columns. The method includes calculating, by the memory controller, an increased Error Correction Code (ECC) layer for each identified codeword based on a number of errors introduced by the bad columns. The method also includes redistributing, by the memory controller, ECC layers from one or more other codewords that have extra ECC layers to increase the ECC layers for the identified codewords with bad columns to enable implementation of the redistributed ECC layers on each codeword in the memory array.

Claims20

Dependent claims

A method for managing error correction in a memory device, the method comprising:

identifying, by a memory controller having an Error Correction Code (ECC) selector, codewords in a memory array of the memory device that are impacted by bad columns detected through testing or monitoring operations;
calculating, by the memory controller, a specific number of additional ECC layers for each identified codeword to correct errors introduced by the bad columns, wherein the specific number is determined by assessing an impact of the bad columns on bits of each identified codeword;
and
redistributing, by the memory controller, ECC layers from one or more other codewords within a same memory page and plane that have extra ECC layers to increase the ECC layers for the identified codewords with bad columns to enable implementation of the redistributed ECC layers on each codeword in the memory array, wherein the redistributing preserves physical locations of data within the memory array.

1 more element

Dependencies are inferred from the claim text.

Memory device bad column identification and compensation

Life of this patent

Memory device bad column identification and compensation

Life of this patent

Abstract

Claims20