Coordinated error protection

An apparatus, comprising:

• a receiver configured to receive, from a memory device, a set of data and an indication of whether the memory device detected one or more errors in the set of data;
• an error management component configured to perform, at a host device, an error management procedure on the set of data received from the memory device to generate a plurality of bits indicating whether one or more errors associated with the set of data were detected at the host device;
• and
• logic configured to:
• receive the indication and a result of the error management component;
• and
• process the set of data based at least in part on the plurality of bits and the indication.

A method, comprising:

• receiving, from a memory device, a set of data and an indication of whether the memory device detected one or more errors in the set of data;
• performing, at a host device, an error management procedure on the set of data received from the memory device to generate a plurality of bits indicating whether one or more errors associated with the set of data were detected at the host device;
• and
• processing the set of data based at least in part on the plurality of bits and the indication.

A non-transitory, computer-readable medium storing code comprising instructions, wherein the instructions are executable by one or more processors to:

• receive, from a memory device, a set of data and an indication of whether the memory device detected one or more errors in the set of data;
• perform, at a host device, an error management procedure on the set of data received from the memory device to generate a plurality of bits indicating whether one or more errors associated with the set of data were detected at the host device;
• and
• process the set of data based at least in part on the plurality of bits and the indication.